1. Field of the Invention
The present invention relates to the design of erasable and programmable non-volatile memory devices; and more particularly to circuits for verifying a programmed or erased state of memory cells in the device, suited for flash EPROM or EEPROM memory cells.
2. Description of Related Art
Non-volatile memory design based on integrated circuit technology represents an expanding field. One popular class of non-volatile memory cell is known as the erasable-programmable read only memory (EPROM). Two popular EPROM designs are distinguished in the manner in which erasure of the memory cells is carried out. The first is referred to as the EEPROM which uses an electrical erasure routine that involves relatively high voltage. A second member of this class is known as the flash EPROM which uses a lower voltage erasing technique.
Both the flash EPROM and EEPROM technologies are based on a memory cell which consists of a source, channel, and drain with a floating gate over the channel and a control gate isolated from the floating gate. The act of programming the cell involves charging the floating gate with electrons, which causes the turn on threshold of the memory cell to increase. Thus, when programmed the cell will not turn on, that is it will remain non-conductive, when addressed with a read potential applied to its control gate. The act of erasing the cell involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate.
Both the flash EPROM and EEPROM memory cells suffer the problem of over-erasure. Over-erasure occurs if, during the erasing step, too many electrons are removed from the floating gate leaving a slight positive charge. This biases the memory cell slightly on, so that a small current may leak through the memory cell even when it is not addressed. A number of over-erased cells along a given bit line can cause an accumulation of leakage current sufficient to cause a false reading. The regular EEPROM design uses a two transistor cell structure which includes a pass gate that isolates the memory cell from the bit line, so that unselected memory cells do not contribute leakage current to the bit line. The flash EPROM cell does not use the isolation transistor, so over-erasure causes a significant problem in the flash EPROM design.
Over-erasure also illustrates an important phenomenon involved with the programming and erasing of floating gate memory cells. That is, the amount of charge which is moved into the floating gate during a given programming phase or moved out of the floating gate during a given erasure phase cannot always be tightly controlled. This amount of charge depends on such factors as the temperature of the cell at the time of the operation, variations in the cells which occur due to processing technology, ceil aging, and other factors.
Therefore, commercial flash EPROM designs include circuitry for verifying the success of programming and erasing steps. See, for instance, U.S. Pat. No. 4,875,188, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM, invented by Jungroth. The prior art devices include a first mode for verifying the programming of the cell during which the potential supplied to the control gate of the cell (across word lines in the memory array) is increased above the normal read potential. Thus, the Jungroth patent provides for applying a 5 V potential to the cell for normal read operations, and a higher potential of approximately 7.5 V during the program verify. By performing program verify with a higher voltage on the control gate, the circuit ensures that the programming step resulted in injection of a sufficient number of electrons into the floating gate to raise the turn on threshold with a safe margin over the minimum amount required. Similarly, during erase verify, the voltage on the control gate is reduced by Jungroth to approximately 3.25 V instead of 5 V. If the cell conducts with 3.25 V applied to its control gate, then it will surely conduct if the read potential of 5 V is applied. Again, this ensures removal of a sufficient amount of charge from the floating gate with a significant margin for safety over the minimum required removal for successful erase.
The standard sensing technology applied to flash EPROM cells involves a differential sense amp which has one input connected to a bit line of a selected cell, and a second input connected to the bit line of a reference cell. The effective resistive load R1 on the bit line of the selected cell and the effective resistive load R2 on the bit line of the reference cell have an effect on the sensing operation known as the sense ratio. Thus, the ratio of R1/R2 determines the ratio of current on the selected cell to current on the reference cell which triggers the sense amp to indicate a conductive state of the memory cell. For instance, a sense ratio of 2.5 will require a current level on the selected bit line of 40% of the current on the reference bit line to indicate a conductive state of the cell.
Prior art systems for verifying programming and erasing, change the level of voltage applied to the control gates of both the memory and reference cells together. To provide further margin, the prior art systems have manipulated the load on the bit lines to affect the sense ratio by increasing the sense ratio from approximately 2.5 to say approximately 4 during program verify. With a sense ratio of 4, a lower level of current on the selected bit line (25% of the current on the reference bit line) is required to trip the sense amp. Similarly, reducing the sense ratio below 2.5 during erase verify is used to increase the amount of current required on the selected bit line to trip the sense amp.
While prior art designs have used a combination of voltage margining on the word lines and sense ratio adjustment based on increasing or decreasing the resistive load of the bit lines, these systems continue to have certain disadvantages. In particular, it is difficult to finely adjust the load of the bit lines to control the sense ratio. This can be done by switching transistors on and off on the load to reduce or increase the resistance. However, the granularity of such techniques is rather crude.
Accordingly, there is a need for an erase verify and program verify circuit for flash EPROMs and other non-volatile memory cells, which allows for finer control of the verify margins involved.